Electronic Trainer / Digital Logic (FPGA) Innovative Development teaching Experimental Box


Product description

Digital logic (FPGA) design innovation development experiment box is a new experimental platform developed by our company to meet the development of electronic technology. The experimental platform is rich in hardware resources, it can meet the requirements of students major in electronic communication to complete the digital logic design course experiment, innovation and development experiment, and the engineering actual algorithm training needs. The platform is equipped with an extensible interface to customize industry specific modules. And the platform performance is stable and cost-effective.

Product Detail

Product composition


Item name




Digital Logic (FPGA) Innovative Development Experiment Box








Double trace digital oscilloscope








JTAG download line




Technical parameters

1. The experiment box adopts the main board plus module structure, and the connector is reliable and easy to upgrade and maintain.

2. FPGA adopts EP4CE22, optional host network port loading, host USB port loading.

3. Display module: 12864 LCD module, TFT color hydraulic crystal module, LED based on SPI bus.

4. Signal module: Generate various signal sources based on STM32F4.

5. Memory module SD card module, I2C bus FLASH, SPI bus (X25045).

6. Modulus and digital-analog conversion module: AD7888, DAC5311.

7. Voice Interface Module: WM8731.

8. Communication interface module: Network port, USB port.

9. Motor measurement and control module: Stepper motor, photoelectric speed measurement.

10. Communication extension module: High speed AD/DA, conversion rate is not less than 200MSPS.


Basic experiments

Basic gate circuit and trigger:

1. Basic Gate Circuit

2. Basic trigger

3. 3-8 Decoder

4. 8-3 Encoder

5. BCD eight-segment display decoder

6. Four selection one data selector

7. Numerical value Comparator

8. 4-bit binary adder

9. 4-bit binary multiplier


Logic circuit

1. Shift register

2. Serial and parallel conversion

3. Single clock synchronous reversible counter

4. Sequence pulse generation and detection

5. Key digital tube circulatory left shift display

6. Electronic clock

7. Key control


FPGA comprehensive application

1. Digital coded lock

2. Intelligence responder

3. Vending machine

4. Digital frequency meter


SOPC system development

1. Building a Qsys environment based on FPGA

2. IO port operation based on Qsys

3. USB communication based on Qsys

4. SD card reading and writing based on Qsys

5. AD conversion based on Qsys

6. DA conversion based on Qsys

7. LCD display based on Qsys (12864 dot matrix and TFT color)

8. network interface based on Qsys

9. Voice interface based on Qsys (WM8731)

10. Comprehensive test based on Qsys


FPGA Communication Technology Application

1. Source encoding and decoding (PAM, PCM, CVSD)

2. Line encoding and decoding (HDB3, AMI, CMI)

3. Code transformation

4. Channel error correction encoding and decoding (Hamming, interleaving, circulation, convolution)

5. Design and update of forming filters and matched filters: Raised cosine, raised square cosine, Gauss

6. Gardner algorithm is adopted for bit synchronization, frame synchronization and timing tracking

7. Carrier tracking adopts Costas rings

8. Multiplexing and demultiplexing

9. Band modulation and demodulation (FSK, PSK, QPSK, QAM, etc.)